From cTuning.org
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| - | ''' | + | <table cellspacing="0" cellpadding="5" border="0" width="100%" style="border: 1px solid rgb(0, 100, 159);"> |
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| + | <tr> | ||
| + | <td width="280" align="center">http://ctuning.org/wiki/images/logo_matmul.gif</td> | ||
| + | <td align="center" valign="center" style="background: rgb(255, 255, 255) none repeat scroll 0% 0%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"> | ||
| + | <font size="5"> | ||
| + | 4th workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion<BR> | ||
| + | (SMART'10) | ||
| + | </font><br><br> | ||
| + | <font size="2"> | ||
| + | <i> | ||
| + | '''January 23, 2010, Pisa, Italy'''<BR><BR> | ||
| + | (co-located with [http://www.hipeac.net/conference HiPEAC 2010 Conference]) | ||
| + | </i> | ||
| + | </font> | ||
| + | </td> | ||
| + | <td width="160" align="left">http://ctuning.org/wiki/images/logo_processor.gif</td> | ||
| + | </tr> | ||
| + | <tr> | ||
| + | <td align="left" valign="top"> | ||
| + | '''Program Chair:''' | ||
| + | * ''[http://www.cs.fsu.edu/~whalley David Whalley]''<BR>Florida State University, USA | ||
| + | |||
| + | '''Program Organizers:''' | ||
| + | * ''[http://fursin.net/research Grigori Fursin]''<BR>INRIA, France | ||
| + | * ''[http://www.cis.udel.edu/~cavazos John Cavazos]''<BR>University of Delaware, USA | ||
| + | |||
| + | '''Program Committee:'''<BR> | ||
| + | <ul>''TBA''</ul> | ||
| + | </td> | ||
| + | <td colspan="2" align="left" valign="top"> | ||
| + | |||
| + | The rapid rate of architectural change and the large diversity | ||
| + | of architecture features has made it increasingly difficult | ||
| + | for compiler writers to keep pace with microprocessor evolution. | ||
| + | This problem has been compounded by the introduction of multicores. | ||
| + | Thus, compiler writers have an intractably complex problem to solve. | ||
| + | A similar situation arises in processor design where new approaches | ||
| + | are needed to help computer architects make the best use of new underlying | ||
| + | technologies and to design systems well adapted to futureapplication domains. | ||
| + | |||
| + | Recent studies have shown the great potential of statistical machine | ||
| + | learning and search strategies for compilation and machine design. | ||
| + | The purpose of this workshop is to help consolidate and advance the state | ||
| + | of the art in this emerging area of research. The workshop is a forum | ||
| + | for the presentation of recent developments in compiler techniques | ||
| + | and machine design methodologies based on space exploration | ||
| + | and statistical machine learning approaches with the objective | ||
| + | of improving performance, parallelism, scalability, and adaptability. | ||
| + | |||
| + | '''Topics of interest include (but are not limited to):'''<BR> | ||
| + | <ul> | ||
| + | Machine Learning, Statistical Approaches, or Search applied to | ||
| + | </ul> | ||
| + | * Feedback-Directed Compilation | ||
| + | * Auto-tuning Programs + Language Extensions | ||
| + | * Library Generators | ||
| + | * Iterative Compilation | ||
| + | * Dynamic Compilation/Adaptive Execution | ||
| + | * Parallel Compiler Optimizations | ||
| + | * Low-power Optimizations | ||
| + | * Simulation | ||
| + | * Performance Models | ||
| + | * Adaptive Processor and System Architecture | ||
| + | * Design Space Exploration | ||
| + | * Other Topics relevant to Intelligent and Adaptive Compilers/Architectures | ||
| + | |||
| + | '''Paper Submission Guidelines:'''<BR> | ||
| + | <ul> | ||
| + | Submitted papers should be original and not published or submitted for publication elsewhere. Papers should use the LNCS format and should be 15 pages maximum. Manuscript preparation guidelines can be found at the [http://www.springer.com/computer/lncs LNCS specification web site] (go to -> For Authors -> Information for LNCS Authors). Submission website will be available soon. | ||
| + | </ul> | ||
| + | |||
| + | '''Important Dates:'''<BR> | ||
| + | <ul> | ||
| + | Final deadline for submission: '''TBA'''<BR> | ||
| + | Decision notification: '''TBA'''<BR> | ||
| + | Workshop: '''Half Day on January 23, 2010'''<BR> | ||
| + | </ul> | ||
| + | |||
| + | '''Previous Workshops:'''<BR> | ||
| + | * [http://www.hipeac.net/smart-workshop.html SMART'09] | ||
| + | * [http://www.hipeac.net/smart-workshop-08.html SMART'08] | ||
| + | * [http://www.hipeac.net/smart-workshop-07.html SMART'07] | ||
| + | |||
| + | </td> | ||
| + | |||
| + | </table> | ||
Revision as of 13:45, 16 July 2009
 |
4th workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion |
 |
|
Program Chair:
Program Organizers:
Program Committee:
|
The rapid rate of architectural change and the large diversity of architecture features has made it increasingly difficult for compiler writers to keep pace with microprocessor evolution. This problem has been compounded by the introduction of multicores. Thus, compiler writers have an intractably complex problem to solve. A similar situation arises in processor design where new approaches are needed to help computer architects make the best use of new underlying technologies and to design systems well adapted to futureapplication domains. Recent studies have shown the great potential of statistical machine learning and search strategies for compilation and machine design. The purpose of this workshop is to help consolidate and advance the state of the art in this emerging area of research. The workshop is a forum for the presentation of recent developments in compiler techniques and machine design methodologies based on space exploration and statistical machine learning approaches with the objective of improving performance, parallelism, scalability, and adaptability. Topics of interest include (but are not limited to):
Paper Submission Guidelines:
Important Dates:
Decision notification: TBA Workshop: Half Day on January 23, 2010 Previous Workshops: |
|