From cTuning.org
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* ''[http://www.cis.udel.edu/~cavazos John Cavazos]''<BR>University of Delaware, USA | * ''[http://www.cis.udel.edu/~cavazos John Cavazos]''<BR>University of Delaware, USA | ||
* ''[http://fursin.net/research Grigori Fursin]''<BR>Exascale Computing Research Center, France | * ''[http://fursin.net/research Grigori Fursin]''<BR>Exascale Computing Research Center, France | ||
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| + | '''Steering Committee:'''<BR> | ||
| + | * ''[http://www.caps-entreprise.com Francois Bodin]''<BR>CAPS Entreprise, France | ||
| + | * ''[http://www.cis.udel.edu/~cavazos John Cavazos]''<BR>University of Delaware, USA | ||
| + | * ''[http://users.elis.ugent.be/~leeckhou Lieven Eeckhout]''<BR>Ghent University, Belgium | ||
| + | * ''[http://fursin.net/research Grigori Fursin]''<BR>INRIA, France | ||
| + | * ''[http://www.dcs.ed.ac.uk/home/mob Michael O'Boyle]''<BR>University of Edinburgh, UK | ||
| + | * ''[http://hpc.cs.uiuc.edu/~padua David Padua]''<BR>UIUC, USA | ||
| + | * ''[http://www.lri.fr/~temam Olivier Temam]''<BR>INRIA, France | ||
| + | * ''[http://vuduc.org Richard Vuduc]''<BR>Georgia Tech, USA | ||
| + | * ''[http://www.cs.fsu.edu/~whalley David Whalley]''<BR>Florida State University, USA | ||
'''Program Committee:'''<BR> | '''Program Committee:'''<BR> | ||
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* ''[http://people.llnl.gov/desupinski1 Bronis R. de Supinski]''<BR>LLNL, USA | * ''[http://people.llnl.gov/desupinski1 Bronis R. de Supinski]''<BR>LLNL, USA | ||
* ''[http://cs.utsa.edu/~qingyi Qing Yi]''<BR>University of Texas at San Antonio, USA | * ''[http://cs.utsa.edu/~qingyi Qing Yi]''<BR>University of Texas at San Antonio, USA | ||
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Revision as of 20:06, 8 December 2010
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5th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion |
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Program Chair:
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Web shortcut: http://cTuning.org/workshop-smart2011 The rapid rate of architectural change and the large diversity of architecture features has made it increasingly difficult for compiler writers to keep pace with microprocessor evolution. This problem has been compounded by the introduction of multicores. Thus, compiler writers have an intractably complex problem to solve. A similar situation arises in processor design where new approaches are needed to help computer architects make the best use of new underlying technologies and to design systems well adapted to future application domains. Recent studies have shown the great potential of statistical machine learning and search strategies for compilation and machine design. The purpose of this workshop is to help consolidate and advance the state of the art in this emerging area of research. The workshop is a forum for the presentation of recent developments in compiler techniques and machine design methodologies based on space exploration and statistical machine learning approaches with the objective of improving performance, parallelism, scalability, and adaptability. Topics of interest include (but are not limited to):
Paper Submission Guidelines:
In addition to normal technical papers, please consider submitting "position paper" (2 to 15 pages). For example, a position paper could include your thoughts on compiler evolution, future infrastructure technology needs, use of adaptive techniques for the Cloud, … An informal collection of the papers to be presented will be distributed at the workshop. All accepted papers will appear on the workshop website. Submission website:
Important Dates:
Previous Workshops: Misc: Sponsors: |
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