From cTuning.org
(Difference between revisions)
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{{CShortCut|workshop-smart2011}} | {{CShortCut|workshop-smart2011}} | ||
| - | The rapid rate of architectural change and the large diversity | + | The rapid rate of architectural change and the large diversity of architecture features has made it increasingly difficult for compiler writers to keep pace with microprocessor evolution. This problem has been compounded by the introduction of multicores. Thus, compiler writers have an intractably complex problem to solve. A similar situation arises in processor design where new approaches are needed to help computer architects make the best use of new underlying technologies and to design systems well adapted to future application domains. |
| - | of architecture features has made it increasingly difficult | + | |
| - | for compiler writers to keep pace with microprocessor evolution. | + | |
| - | This problem has been compounded by the introduction of multicores | + | |
| - | Thus, compiler writers have an intractably complex problem to solve. | + | |
| - | A similar situation arises in processor design where new approaches | + | |
| - | are needed to help computer architects make the best use of new underlying | + | |
| - | technologies and to design systems well adapted to future application domains. | + | |
| - | Recent studies have shown the great potential of statistical machine | + | Recent studies have shown the great potential of statistical machine learning and search strategies for compilation and machine design. The purpose of this workshop is to help consolidate and advance the state of the art in this emerging area of research. The workshop is a forum for the presentation of recent developments in compiler techniques and machine design methodologies based on space exploration and statistical machine learning approaches with the objective of improving performance, parallelism, scalability, and adaptability. |
| - | learning and search strategies for compilation and machine design. | + | |
| - | The purpose of this workshop is to help consolidate and advance the state | + | |
| - | of the art in this emerging area of research. The workshop is a forum | + | |
| - | for the presentation of recent developments in compiler techniques | + | |
| - | and machine design methodologies based on space exploration | + | |
| - | and statistical machine learning approaches with the objective | + | |
| - | of improving performance, parallelism, scalability, and adaptability. | + | |
'''Topics of interest include (but are not limited to):'''<BR> | '''Topics of interest include (but are not limited to):'''<BR> | ||
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* Low-power Optimizations | * Low-power Optimizations | ||
* Adaptive Virtualization | * Adaptive Virtualization | ||
| - | * Performance Modeling | + | * Performance Modeling and Portability |
| - | + | ||
* Adaptive Processor and System Architecture | * Adaptive Processor and System Architecture | ||
* Architecture Simulation and Design Space Exploration | * Architecture Simulation and Design Space Exploration | ||
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'''Paper Submission Guidelines:'''<BR> | '''Paper Submission Guidelines:'''<BR> | ||
<ul> | <ul> | ||
| - | Submitted papers should be original and not published or submitted for publication elsewhere. Papers should use the LNCS format and should be 15 pages maximum. Manuscript preparation guidelines can be found at the [http://www.springer.com/computer/lncs LNCS specification web site] (go to -> For Authors -> Information for LNCS Authors). Papers must be submitted in the PDF format.<BR><BR> | + | Submitted papers should be original and not published or submitted for publication elsewhere. Papers should use the LNCS format and should be 15 pages maximum. Manuscript preparation guidelines can be found at the [http://www.springer.com/computer/lncs LNCS specification web site] (go to -> For Authors -> Information for LNCS Authors). Papers must be submitted in the PDF format using the workshop submission website.<BR><BR> |
| + | |||
| + | <span style="color:#FF0000"> | ||
| + | In addition to normal technical papers, please consider submitting "position paper" (2 to 15 pages). For example, a position paper could include your thoughts on compiler evolution, future infrastructure technology needs, use of adaptive techniques for the Cloud, … | ||
| + | </span> | ||
| + | |||
An informal collection of the papers to be presented will be distributed at the workshop. All accepted papers will appear on the workshop website. | An informal collection of the papers to be presented will be distributed at the workshop. All accepted papers will appear on the workshop website. | ||
</ul> | </ul> | ||
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<ul> | <ul> | ||
{|border="0" cellpadding="4" cellspacing="0" | {|border="0" cellpadding="4" cellspacing="0" | ||
| - | |||
| - | |||
| - | |||
|- | |- | ||
|Deadline for paper submission: | |Deadline for paper submission: | ||
| - | | | + | | Feburary 7, 2011 |
|- | |- | ||
|Decision notification: | |Decision notification: | ||
| - | | | + | | March 7, 2011 |
|- | |- | ||
|Deadline for camera-ready papers: | |Deadline for camera-ready papers: | ||
| - | | | + | |March 25, 2011 |
|- | |- | ||
|Workshop: | |Workshop: | ||
| - | | ''' | + | | '''April 2 or 3, 2011''' (half-day)<BR> |
|} | |} | ||
</ul> | </ul> | ||
'''Previous Workshops:'''<BR> | '''Previous Workshops:'''<BR> | ||
| - | * [ | + | * [http://cTuning.org/workshop-smart10 SMART'10] |
* [http://www.hipeac.net/smart-workshop.html SMART'09] | * [http://www.hipeac.net/smart-workshop.html SMART'09] | ||
* [http://www.hipeac.net/smart-workshop-08.html SMART'08] | * [http://www.hipeac.net/smart-workshop-08.html SMART'08] | ||
Revision as of 21:42, 7 December 2010
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5th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion |
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Program Chair:
Workshop Organizers:
Steering Committee:
Program Committee: |
Web shortcut: http://cTuning.org/workshop-smart2011 The rapid rate of architectural change and the large diversity of architecture features has made it increasingly difficult for compiler writers to keep pace with microprocessor evolution. This problem has been compounded by the introduction of multicores. Thus, compiler writers have an intractably complex problem to solve. A similar situation arises in processor design where new approaches are needed to help computer architects make the best use of new underlying technologies and to design systems well adapted to future application domains. Recent studies have shown the great potential of statistical machine learning and search strategies for compilation and machine design. The purpose of this workshop is to help consolidate and advance the state of the art in this emerging area of research. The workshop is a forum for the presentation of recent developments in compiler techniques and machine design methodologies based on space exploration and statistical machine learning approaches with the objective of improving performance, parallelism, scalability, and adaptability. Topics of interest include (but are not limited to):
Paper Submission Guidelines:
In addition to normal technical papers, please consider submitting "position paper" (2 to 15 pages). For example, a position paper could include your thoughts on compiler evolution, future infrastructure technology needs, use of adaptive techniques for the Cloud, … An informal collection of the papers to be presented will be distributed at the workshop. All accepted papers will appear on the workshop website. Submission website:
Important Dates:
Previous Workshops: Misc: Sponsors: |
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